JOB: DDR Lead Verification Engineer at Cadence



Location: Bengaluru and Pune

Firm: Cadence

Place Description:

  • Purposeful Verification Engineer for DDR Reminiscence Controller and PHY IP growth staff.
  • The place is predicated in Bangalore.
  • The position would come with practical verification of the DDR Reminiscence Controller and PHY IP resolution of Cadence.
  • The work concerned can be working with the present practical verification surroundings, the addition of latest options into the verification surroundings, making certain varied buyer configurations are clear as a part of verification regressions, supporting prospects in case of any points with utilizing the verification surroundings, and practical and code protection.
  • The engineer can be accountable to make sure that the design is according to the technical and high quality necessities set for the staff – notably with respect to practical and code protection.

Place Necessities:

    • BE/BTech/ME/MTech – Electrical / Electronics / VLSI with expertise as a design and verification engineer, with a big portion of the current work expertise on verification surroundings growth.
    • Sturdy background in practical verification fundamentals, surroundings planning, check plan era, and surroundings growth is a should.
    • System Verilog expertise and expertise with UVM-based practical verification surroundings growth are required.
    • Prior RTL Design expertise utilizing Verilog is a should – in order that the verification engineer is self-sufficient for many facets of debugging.
    • The Newest DDR Protocol expertise is extremely fascinating. Prior expertise in practical verification and debugging of complicated protocols is a should.
    • AXI3/4 expertise is fascinating.
    • Prior expertise in IP growth groups can be an added benefit.



Please enter your comment!
Please enter your name here